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1996 preliminary product information mos integrated circuit m pd784214y,784215y,784216y 16/8-bit single-chip microcontrollers the m PD784216Y is based on the m pd784216 with an i 2 c bus control function appended, and is ideal for applications in audio-visual. flash memory versions, such as m pd78f4216y, that can operate in the same voltage range as the mask rom version, and various development tools are under development. the functions are explained in detail in the following users manuals. be sure to read this manual when designing your system. m pd784216, 784216y subseries users manual - hardware: planned 78k/iv series users manual - instruction : u10905e features ? 78k/iv series ? inherits peripheral functions of upd78078y subseries ? pin-compatible with m pd784216 subseries ? minimum instruction execution time 160 ns (main system clock f xx = 12.5 mhz) 61 m s (subsystem clock f xt = 32.768 khz) ? i/o port: 86 pins ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 6 units ? serial interface: 3 channels uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o, multi-master supporting i 2 c bus): 1 channel ? standby function halt/stop/idle mode in power-saving mode: halt/idle mode (with subsystem clock) ? clock division function ? watch timer: 1 channel ? watchdog timer: 1 channel ? clock output function f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt selectable ? buzzer output function f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 selectable ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? supply voltage: v dd = 1.8 to 5.5 v document no. u11725ej1v0pm00 (1st edition) date published september 1996 p printed in japan the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. application field cullular telephones, phs, cordless telephones, cd-rom, av systems unless contextually excluded, references in this document to m PD784216Y mean m pd784214y, m pd784215y, and m PD784216Y.
2 m pd784214y,784215y,784216y ordering information part number package internal rom (bytes) internal ram (bytes) m pd784214ygc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 96 k 3584 m pd784214ygf- -3ba 100-pin plastic qfp (14 20 mm) 96 k 3584 m pd784215ygc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 128 k 5120 m pd784215ygf- -3ba 100-pin plastic qfp (14 20 mm) 128 k 5120 m PD784216Ygc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 128 k 8192 m PD784216Ygf- -3ba 100-pin plastic qfp (14 20 mm) 128 k 8192 remark indicates a rom code suffix. 78k/iv series product development : under mass production : under development standard models pd784026 subseries m 80 pins, 8-bit a/d, 8-bit d/a rom : none/48k/64k pd784038y subseries m i 2 c bus supporting models pd784038 subseries m 80 pins, 8-bit a/d, 8-bit d/a rom : none/48k/64k/96k/128k PD784216Y subseries m i 2 c bus supporting models pd784216 subseries m 100 pins, 8-bit a/d, 8-bit d/a rom : 96k/128k pd784054 m 80 pins, 10-bit a/d, rom : 32k pd784046 subseries subset pd784915 subseries m vcr servo, 100 pins, analog amplifier rom : 48k/62k assp models pd784046 subseries m 80 pins, 10-bit a/d rom : 32k/64k m pd784908 subseries m 100 pins, iebus tm controller rom : 96k/128k pd78f4943 subseries m 80 pins, for cd-rom flash memory: 56k
3 m pd784214y,784215y,784216y functions (1/2) part number m pd784214y m pd784215y m PD784216Y item number of basic instructions 113 (mnemonics) general-purpose register 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution ? 160 ns/320 ns/640 ns/1280 ns/2560 ns (main system clock = 12.5 mhz) time ? 61 m s (subsystem clock = 32.768 khz) internal rom 96 kbytes 128 kbytes memory ram 3584 bytes 5120 bytes 8192 bytes memory space 1 mb with program and data spaces combined i/o port total 86 cmos input 8 cmos i/o 72 n-ch open-drain i/o 6 pins with pull-up 70 resistor leds direct 22 drive output medium 6 voltage pin real-time output port 4 bits 2, or 8 bits 1 timer/counter 16-bit timer/counter : timer register 1 pulse output capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output 8-bit timer/counter 1 : timer register 1 pulse output compare register 1 ? pwm output ? square wave output 8-bit timer/counter 2 : timer register 1 pulse output compare register 1 ? pwm output ? square wave output 8-bit timer/counter 5 : timer register 1 pulse output compare register 1 ? pwm output ? square wave output 8-bit timer/counter 6 : timer register 1 pulse output compare register 1 ? pwm output ? square wave output 8-bit timer/counter 7 : timer register 1 pulse output compare register 1 ? pwm output ? square wave output 8-bit timer/counter 8 : timer register 1 pulse output compare register 1 ? pwm output ? square wave output note the pins with ancillary functions are included in the i/o pins. pins with ancillary functions note
4 m pd784214y,784215y,784216y functions (2/2) part number m pd784214y m pd784215y m PD784216Y item serial interface uart/ioe (3-wire serial i/o): 2 channels ( on-chip baud rate generator ) csi (3-wire serial i/o, i 2 c bus supporting multi master): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel standby ? halt/stop/idle mode ? in power-saving mode (with subsystem clock): halt/idle mode interrupt source 29 (internal: 20, external: 9) + brk instruction software brk instruction non-maskable internal: 1, external: 1 maskable internal: 19, external: 8 ? 4 programmable priority levels ? 3 service modes: vectored interrupt/macro service/context switching supply voltage v dd = 1.8 to 5.5 v package 100-pin plastic qfp (fine pitch) (14 14 mm) 100-pin plastic qfp (14 20 mm)
5 m pd784214y,784215y,784216y contents 1. differences among models in m m m m m PD784216Y subseries ............................................. 7 2. main differences from m m m m m pd78078y subseries ............................................................. 8 3. pin configuration (top view) .............................................................................................. 9 4. block diagram ......................................................................................................................... 12 5. pin function .............................................................................................................................. 13 5.1 port pins ................................................................................................................................................ 13 5.2 pins other than port pins .................................................................................................................. 15 5.3 i/o circuit type of respective pins and recommended connections of unused pins ........... 17 6. cpu architecture ................................................................................................................... 20 6.1 memory space ...................................................................................................................................... 20 6.2 cpu registers ...................................................................................................................................... 24 6.2.1 general-purpose registers ........................................................................................................ 24 6.2.2 control registers ........................................................................................................................ 25 6.2.3 special function registers (sfrs) ............................................................................................. 26 7. peripheral hardware functions ................................................................................... 31 7.1 ports ....................................................................................................................................................... 31 7.2 clock generation circuit ..................................................................................................................... 32 7.3 real-time output port ......................................................................................................................... 34 7.4 timer/counter ....................................................................................................................................... 35 7.5 a/d converter ....................................................................................................................................... 38 7.6 d/a converter ....................................................................................................................................... 39 7.7 serial interface ..................................................................................................................................... 40 7.7.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) .................................................. 41 7.7.2 clocked serial interface (csi) .................................................................................................... 43 7.8 clock output function ........................................................................................................................ 44 7.9 buzzer output function ...................................................................................................................... 45 7.10 edge detection function .................................................................................................................... 45 7.11 watch timer .......................................................................................................................................... 45 7.12 watchdog timer ................................................................................................................................... 46 8. interrupt function ............................................................................................................... 47 8.1 interrupt sources ................................................................................................................................. 47 8.2 vectored interrupt ................................................................................................................................ 49 8.3 context switching ................................................................................................................................ 50 8.4 macro service ....................................................................................................................................... 50 8.5 application example of macro service ............................................................................................. 51
6 m pd784214y,784215y,784216y 9. local bus interface ............................................................................................................. 52 9.1 memory expansion .............................................................................................................................. 53 9.2 programmable wait ............................................................................................................................. 53 10. standby function ................................................................................................................... 54 11. reset function ........................................................................................................................ 56 12. instruction set ....................................................................................................................... 57 13. package drawings ................................................................................................................. 62 appendix a. development tools ............................................................................................ 64 appendix b. related documents ............................................................................................ 66
7 m pd784214y,784215y,784216y 1. differences among models in m m m m m PD784216Y subseries the only difference among the m pd784214y, 784215y, and 784216y lies in the internal memory capacity. the m pd78p4216y is provided with a 128-kb flash memory instead of the mask rom of the above models. these differences are summarized in table 1-1. table 1-1. differences among models in m m m m m PD784216Y subseries part number m pd784214y m pd784215y m PD784216Y m pd78f4216y item internal rom 96 kbytes 128 kbytes 128 kbytes (mask rom) (mask rom) (flash memory) internal ram 3584 bytes 5120 bytes 8192 bytes internal memory none provided size switching register (ims) v pp pin none provided
8 m pd784214y,784215y,784216y 2. main differences from m m m m m pd78078y subseries series name m PD784216Y subseries m pd78078y subseries item cpu 16-bit cpu 8-bit cpu minimum instruction with main 160 ns (at 12.5 mhz) 400 ns (at 5.0 mhz) execution time system clock with subsystem 61 m s (at 32.768 khz) 122 m s (32.768 khz) clock memory space 1 mbytes 64 kbytes i/o port total 88 88 cmos input 8 2 cmos i/o 72 78 n-ch open-drain i/o 6 8 pins with ancillary pins with pull-up 70 86 functions note resistor led direct drive 22 16 output medium-voltage pin 6 8 timer/counter ? 16-bit timer/counter 1 unit ? 16-bit timer/counter 1 unit ? 8-bit timer/counter 6 units ? 8-bit timer/counter 4 units serial interface ? uart/ioe (3-wire serial i/o) ? uart/ioe (3-wire serial i/o) 2 channels 1 channel ? csi (3-wire serial i/o, multi-master ? csi (3-wire serial i/o, 2-wire serial supporting i 2 c bus) 1 channel i/o, i 2 c bus) 1 channel ? csi (3-wire serial i/o, 3-wire serial i/o with automatic transmit/receive function) 1 channel interrupt nmi pin provided none macro service provided none context switching provided none programmable priority 4 levels none standby function 3 modes: halt/stop/idle 2 modes: halt/stop package ? 100-pin plastic qfp (fine pitch) ? 100-pin plastic qfp (14 20 mm) (14 14 mm) ? ceramic wqfn (14 20 mm) ? 100-pin plastic qfp (14 20 mm) ( m pd78p078y only) note the pins with ancillary functions are included in the i/o pins.
9 m pd784214y,784215y,784216y 3. pin configuration (top view) ? 100-pin plastic qfp (fine pitch) (14 14 mm) m m m m m pd784214ygc- -7ea m m m m m pd784215ygc- -7ea m m m m m PD784216Ygc- -7ea notes 1. directly connect the test pin to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20? 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 76 p120/rtp0 p121/rtp1 p122/rtp2 p123/rtp3 p124/rtp4 p125/rtp5 p126/rtp6 p127/rtp7 v dd x2 x1 v ss xt2 xt1 reset p00/intp0 p01/intp1 p02/intp2/nmi p03/intp3 p04/intp4 p05/intp5 p06/intp6 av dd notes 2 av ref0 p10/ani0 p62/a18 p61/a17 p60/a16 v ss p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p87/a7 p86/a6 p85/a5 p84/a4 p83/a3 p95 p94 p93 p92 p91 p90 test notes 1 p37 p36/ti01 p35/ti00 p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103/ti8/to8 p102/ti7/to7 p101/ti6/to6 p100/ti5/to5 v dd p67/astb p66/wait p65/wr p64/rd p63/a19 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss notes 3 p130/ano0 p131/ano1 av ref1 p70/rxd2/si2 p71/txd2/so2 p72/asck2/sck2 p20/rxd1/si1 p21/txd1/so1 p22/asck1/sck1 p23/pcl p24/buz p25/si0/sda0 p26/so0 p27/sck0/scl0 p80/a0 p81/a1 p82/a2 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 m pd784214y,784215y,784216y ? 100-pin plastic qfp (14 20 mm) m m m m m pd784214ygf- -3ba m m m m m pd784215ygf- -3ba m m m m m PD784216Ygf- -3ba 100 v ss p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p87/a7 p86/a6 p85/a5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p84/a4 p83/a3 p82/a2 p81/a1 p80/a0 p27/sck0/scl0 p26/so0 p25/si0/sda0 p24/buz p23/pcl p22/asck1/sck1 p21/txd1/so1 p20/rxd1/si1 p72/asck2/sck2 p71/txd2/so2 p70/rxd2/si2 av ref1 p131/ano1 p130/ano0 av ss notes 3 p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd notes 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20? 21 22 23 24 25 26 27 28 29 30 p60/a16 p61/a17 p62/a18 p63/a19 p64/rd p65/wr p66/wait p67/astb v dd p100/ti5/to5 p101/ti6/to6 p102/ti7/to7 p103/ti8/to8 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/ti00 p36/ti01 p37 test notes 1 p90 p91 p92 p93 p94 p95 p120/rtp0 p121/rtp1 p122/rtp2 p123/rtp3 p124/rtp4 p125/rtp5 p126/rtp6 p127/rtp7 v dd x2 x1 v ss xt2 xt1 reset p00/intp0 p01/intp1 p02/intp2/nmi p03/intp3 p04/intp4 p05/intp5 p06/intp6 31 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 notes 1. directly connect the test pin to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss .
11 m pd784214y,784215y,784216y p00-p06 : port0 scl0 : serial clock p10-p17 : port1 rxd1, rxd2 : receive data p20-p27 : port2 txd1, txd2 : transmit data p30-p37 : port3 asck1, asck2 : asynchronous serial clock p40-p47 : port4 pcl : programmable clock p50-p57 : port5 buz : buzzer clock p60-p67 : port6 ad0-ad7 : address/data bus p70-p72 : port7 a0-a19 : address bus t80-p87 : port8 rd : read strobe p90-p95 : port9 wr : write strobe p100-p103 : port10 wait : wait p120-p127 : port12 astb : address strobe p130, p131 : port13 x1, x2 : crystal (main system clock) rtp0-rtp7 : real-time output port xt1, xt2 : crystal (subsystem clock) nmi : non-maskable interrupt reset : reset intp0-intp6 : interrupt from peripherals ani0-ani7 : analog input ti00, ti01 : timer input ano0, ano1 : analog output ti1, ti2, ti5-ti8 : timer input av dd : analog power supply to0-to2, to5-to8 : timer output av ss : analog ground si0-si2 : serial input av ref0 , av ref1 : analog reference voltage so0-so2 : serial output v dd : power supply sda0 : serial data v ss : ground sck0-sck2 : serial clock test : test
12 m pd784214y,784215y,784216y 4. block diagram intp2/nmi intp0, intp1, intp3-intp6 programmable interrupt controller real-time output port timer/counter7 (8 bits) timer/counter6 (8 bits) timer/counter5 (8 bits) timer/counter2 (8 bits) timer/counter1 (8 bits) timer/counter (16 bits) watch timer timer/counter8 (8 bits) watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 ti5/to5 ti6/to6 ti7/to7 ti8/to8 rtp0-rtp7 clock output control a/d converter av dd av ss pcl buz av ref0 ani0-ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 si0/sda0 so0 sck0/scl0 bus i/f uart/ioe1 rd astb wr wait a0-a7 ad0-ad7 a8-a15 a16-a19 port1 p10-p17 port0 p00-p06 port2 p20-p27 port3 p30-p37 port4 p40-p47 port5 p50-p57 port6 p60-p67 port7 p70-p72 port8 p80-p87 port9 p90-p95 port10 p100-p103 port12 p120-p127 port13 p130,p131 buzzer output system control reset xt2 x1 xt1 x2 v ss v dd test clocked serial interface baud-rate generator uart/ioe2 remark the internal rom and ram capacities differ depending on the model.
13 m pd784214y,784215y,784216y 5. pin function 5.1 port pins (1/2) pin name i/o alternate function function p00 i/o intp0 p01 intp1 p02 intp2/nm1 p03 intp3 p04 intp4 p05 intp5 p06 intp6 p10-p17 input ani0-ani7 p20 i/o rxd1/si1 p21 txd1/so1 p22 asck1/sck1 p23 pcl p24 buz p25 si0/sda0 p26 so0 p27 sck0/scl0 p30 i/o to0 p31 to1 p32 to2 p33 ti1 p34 ti2 p35 ti00 p36 ti01 p37 p40-p47 i/o ad0-ad7 port 4 (p4): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? all pins set in input mode can be connected to internal pull-up resistors by software. ? can drive leds. p50-p57 i/o a8-a15 port 5 (p5): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? all pins set in input mode can be connected to internal pull-up resistors by software. ? can drive leds. port 1 (p1): ? 8-bit input port port 0 (p0): ? 7-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistors by software bit-wise. port 2 (p2): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistors by software bit-wise. port 3 (p3): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistors by software bit-wise.
14 m pd784214y,784215y,784216y 5.1 port pins (2/2) pin name i/o alternate function function p60 i/o a16 p61 a17 p62 a18 p64 rd p65 wr p66 wait p67 astb p70 i/o rxd2/si2 p71 txd2/so2 p72 asck2/sck2 p80-p87 i/o a0-a7 port 8 (p8): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistor by software bit-wise. ? interrupt control flag (krif) is set to 1 when falling edge is detected at a pin of this port. p90-p95 i/o port 9 (p9): ? n-ch open-drain medium-voltage i/o port ? 6-bit i/o port ? can be set in input or output mode bit-wise. ? can directly drive leds. p100 i/o ti5/to5 p101 ti6/to6 p102 ti7/to7 p103 ti8/to8 p120-p127 i/o rtp0-rtp7 port 12 (p12): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistor by software bit-wise. p130, p131 i/o ano0, ano1 port 13 (p13): ? 2-bit i/o port ? can be set in input or output mode bit-wise. port 6 (p6): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? all pins set in input mode can be connected to internal pull-up resistors by software. port 7 (p7): ? 3-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistor by software bit-wise. port 10 (p10): ? 4-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistor by software bit-wise.
15 m pd784214y,784215y,784216y 5.2 pins other than port pins (1/2) pin name i/o alternate function function ti00 input p35 external count clock input to 16-bit timer register ti01 p36 capture trigger signal input to capture/compare register 00 ti1 p33 external count clock input to 8-bit timer register 1 ti2 p34 external count clock input to 8-bit timer register 2 ti5 p100/to5 external count clock input to 8-bit timer register 5 ti6 p101/to6 external count clock input to 8-bit timer register 6 ti7 p102/to7 external count clock input to 8-bit timer register 7 ti8 p103/to8 external count clock input to 8-bit timer register 8 to0 output p30 16-bit timer output (shared by 14-bit pwm output) to1 p31 8-bit timer output (shared by 8-bit pwm output) to2 p32 to5 p100/ti5 to6 p101/ti6 to7 p102/ti7 to8 p103/ti8 rxd1 input p20/si1 serial data input (uart1) rxd2 p70/si2 serial data input (uart2) txd1 output p21/so1 serial data output (uart1) txd2 p71/so2 serial data output (uart2) asck1 intput p22/sck1 baud rate clock input (uart1) asck2 p72/sck2 baud rate clock input (uart2) si0 input p25/sda0 serial data input (3-wire serial clock i/o0) si1 p20/rxd1 serial data input (3-wire serial clock i/o1) si2 p70/rxd2 serial data input (3-wire serial clock i/o2) so0 output p26 serial data output (3-wire serial i/o0) so1 p21/txd1 serial data output (3-wire serial i/o1) so2 p71/txd2 serial data output (3-wire serial i/o2) sda0 i/o p25/si0 serial data input/output (i 2 c bus) sck0 i/o p27/scl0 serial clock input/output (3-wire serial i/o0) sck1 p22/asck1 serial clock input/output (3-wire serial i/o1) sck2 p72/asck2 serial clock input/output (3-wire serial i/o2) scl0 p27/sck0 serial clock input/output (i 2 c bus) nmi input p02/intp2 non-maskable interrupt request input intp0 p00 external interrupt request input intp1 p01 intp2 p02/nmi intp3 p03 intp4 p04 intp5 p05 intp6 p06
16 m pd784214y,784215y,784216y 5.2 pins other than port pins (2/2) pin name i/o alternate function function pcl output p23 clock output (for trimming main system clock and subsystem clock) buz output p24 buzzer output rtp0-rtp7 output p120-p127 real-time output port that outputs data in synchronization with trigger ad0-ad7 i/o p40-p47 low-order address/data bus when external memory is connected a0-a7 output p80-p87 low-order address bus when external memory is connected a8-a15 p50-p57 middle-order address bus when external memory is connected a16-a19 p60-p63 high-order address bus when external memory is connected rd output p64 strobe signal output for read operation of external memory wr p65 strobe signal output for write operation of external memory wait input p66 to insert wait state(s) when external memory is accessed astb output p67 strobe output to externally latch address information output to ports 4 through 6 and port 8 to access external memory reset input system reset input x1 input to connect main system clock oscillation crystal x2 xt1 input to connect subsystem clock oscillation crystal xt2 ani0-ani7 input p10-p17 analog voltage input for a/d converter ano0, ano1 output p130, p131 analog voltage output for d/a converter av ref0 to apply reference voltage for a/d converter av ref1 to apply reference voltage for d/a converter av dd positive power supply for a/d converter. connected to v dd . av ss gnd for a/d converter and d/a converter. connected to v ss . v dd positive power supply v ss gnd test directly connect this pin to v ss (this pin is for ic test).
17 m pd784214y,784215y,784216y 5.3 i/o circuit type of respective pins and recommended connections of unused pins table 5-1 shows symbols indicating the i/o circuit types of the respective pins and the recommended connection of unused pins. for the circuit diagram of each type of i/o circuit, refer to figure 5-1 . table 5-1. i/o circuit type of respective pins and recommended connections of unused pins (1/2) pin name i/o circuit type i/o recommended connections of unused pins p00/intp0 8-a i/o input : individually connected to v ss via resistor p01/intp1 output: open p02/intp2/nmi p03/intp3-p06/intp6 p10/ani0-p17/ani7 11 input connected to v ss or v dd p20/rxd1/si1 10-a i/o input : individually connected to v ss via resistor p21/txd1/so1 output: open p22/asck1/sck1 p23/pcl p24/buz p25/sda0/si0 p26/so0 p27/scl0/sck0 p30/to0-p32/to2 8-a p33/ti1, p34/ti2 p35/ti00, p36/ti01 p37 p40/ad0-p47/ad7 5-a p50/a8-p57/a15 p60/a16-p63/a19 p64/rd p65/wr p66/wait p67/astb p70/rxd2/si2 8-a p71/txd2/so2 p72/asck2/sck2 p80/a0-p87/a7 p90-p95 13-d p100/ti5/to5 8-a p101/ti6/to6 p102/ti7/to7 p103/ti8/to8 p120/rtp0-p127/rtp7 p130/ano0, p131/ano1 12-a
18 m pd784214y,784215y,784216y table 5-1. i/o circuit type of respective pins and recommended connections of unused pins (2/2) pin name i/o circuit type i/o recommended connections of unused pins reset 2 input xt1 16 connected to v ss xt2 open av ref0 connected to v ss av ref1 connected to v dd av dd av ss connected to v ss test directly connected to v ss remark because the circuit type numbers are standardized among the 78k series products, they are not sequential in some models (i.e., some circuits are not provided).
19 m pd784214y,784215y,784216y figure 5-1. types of pin i/o circuits type 2 in schmitt trigger input with hysteresis characteristics type 5-a pullup enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch type 8-a pullup enable data output disable v dd p-ch v dd p-ch in/out n-ch type 10-a pullup enable data open drain output disable v dd p-ch v dd p-ch in/out n-ch type 11 pullup enable data output disable comparator input enable v dd p-ch v dd p-ch in/out n-ch p-ch n-ch v ref (threshold voltage) + type 12-a pullup enable data output disable input enable analog output voltage v dd p-ch v dd p-ch in/out n-ch p-ch n-ch type 13-d data output disable rd in/out n-ch v dd p-ch medium-voltage input buffer type 16 feedback cut-off p-ch xt1 xt2
20 m pd784214y,784215y,784216y 6. cpu architecture 6.1 memory space a memory space of 1 mbyte can be accessed. mapping of the internal data area (special function registers and internal ram) can be specified the location instruction. the location instruction must be always executed after reset cancellation, and must not be used more than once. (1) when location 0 instruction is executed ? internal memory the internal data area and internal rom area are mapped as follows: part number internal data area internal rom area m pd784214y 0f100h-0ffffh 00000h-0f0ffh 10000h-17fffh m pd784215y 0eb00h-0ffffh 00000h-0eaffh 10000h-1ffffh m PD784216Y 0df00h-0ffffh 00000h-0deffh 10000h-1ffffh caution the following areas that overlap the internal data area of the internal rom cannot be used when the location 0 instruction is executed. part number unusable area m pd784214y 0f100h-0ffffh (3840 bytes) m pd784215y 0eb00h-0ffffh (5376 bytes) m PD784216Y 0df00h-0ffffh (8448 bytes) ? external memory the external memory is accessed in external memory expansion mode. (2) when location 0fh instruction is executed ? internal memory the internal data area and internal rom area are mapped as follows: part number internal data area internal rom area m pd784214y ff100h-fffffh 00000h-17fffh m pd784215y feb00h-fffffh 00000h-1ffffh m PD784216Y fdf00h-fffffh 00000h-1ffffh ? external memory the external memory is accessed in external memory expansion mode.
21 m pd784214y,784215y,784216y notes 1. accessed in external memory expansion mode. 2. this 3840-byte area can be used as an internal rom only when the location 0fh instruction is executed. 3. on execution of location 0 instruction: 94464 bytes, on execution of location 0fh instruction: 98304 bytes 4. base area and entry area for reset or interrupt. however, the internal ram area is not used as a reset entry area. figure 6-1. memory map of m m m m m pd784214y internal rom (61696 bytes) (256 bytes) special function registers (sfr) internal ram (3584 bytes) external memory note 1 (928 kbytes) note 1 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (3072 bytes) callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (3584 bytes) external memory note 1 (980736 bytes) (256 bytes) internal rom (96 kbytes) on execution of location 0 instruction special function registers (sfr) note 1 on execution of location 0fh instruction h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 1 f 0 h f f 0 f 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h b 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 1 f 0 h f f f 7 1 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h b 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 7 f f h 0 0 0 0 0 h f f f 7 1 h 0 0 0 8 1 h f f 0 f f h 0 0 1 f f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 note 2 h f f f 7 1 h 0 0 0 8 1 h f f f 7 1 internal rom (32768 bytes) h f f 0 f 0 h 0 0 0 0 1
22 m pd784214y,784215y,784216y figure 6-2. memory map of m m m m m pd782157y notes 1. accessed in external memory expansion mode. 2. this 5376-byte area can be used as an internal rom only when the location 0fh instruction is executed. 3. on execution of location 0 instruction: 125696 bytes, on execution of location 0fh instruction: 131072 bytes 4. base area and entry area for reset or interrupt. however, the internal ram area is not used as a reset entry area. internal rom (60160 bytes) (256 bytes) special function registers (sfr) internal ram (5120 bytes) external memory note 1 (896kbytes) note 1 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (4608 bytes) callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (5120 bytes) external memory note 1 (912128 bytes) (256 bytes) internal rom (128 kbytes) on execution of location 0 instruction special function registers (sfr) note 1 on execution of location 0fh instruction h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 b e 0 h f f a e 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h b 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 b e 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h b 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 b e f h 0 0 0 0 0 h f f f f 1 h 0 0 0 0 2 h f f a e f h 0 0 b e f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 h f f f f 1 internal rom (65536 bytes) h 0 0 0 0 2 h f f f f 1 h f f f f 1 note 2 h f f a e 0 h 0 0 0 0 1
23 m pd784214y,784215y,784216y figure 6-3. memory map of m m m m m PD784216Y notes 1. accessed in external memory expansion mode. 2. this 8448-byte area can be used as an internal rom only when the location 0fh instruction is executed. 3. on execution of location 0 instruction: 122624 bytes, on execution of location 0fh instruction: 131072 bytes 4. base area and entry area for reset or interrupt. however, the internal ram area is not used as a reset entry area. internal rom (57088 bytes) (256 bytes) special function registers (sfr) internal ram (8192 bytes) external memory note 1 (896 kbytes) note 1 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (7680 bytes) callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (8192 bytes) external memory note 1 (909056 bytes) (256 bytes) internal rom (128 kbytes) on execution of location 0 instruction special function registers (sfr) note 1 on execution of location 0fh instruction h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 f d 0 h f f e d 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h b 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 f d 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h b 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 f d f h 0 0 0 0 0 h f f f f 1 h 0 0 0 0 2 h f f e d f h 0 0 f d f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 h 0 0 0 0 2 h f f f f 1 h f f f f 1 internal rom (65536 bytes) h f f f f 1 note 2 h f f e d 0 h 0 0 0 0 1
24 m pd784214y,784215y,784216y 6.2 cpu registers 6.2.1 general-purpose registers sixteen 8-bit general-purpose registers are available. two 8-bit registers can be also used in pairs as a 16-bit register. of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. eight banks of these registers are available which can be selected by using software or the context switching function. the general-purpose registers except v, u, t, and w registers for address expansion are mapped to the internal ram. figure 6-4. general-purpose register format a (r1) b (r3) r5 r7 r9 r11 d (r13) h (r15) v u t w vvp (rg4) uup (rg5) tde (rg6) whl (rg7) x (r0) c (r2) r4 r6 r8 r10 e (r12) l (r14) ax (rp0) bc (rp1) rp2 rp3 vp (rp4) up (rp5) de (rp6) hl (rp7) parentheses ( ) indicate an absolute name. 8 banks caution registers r4, r5, r6, r7, rp2, and rp3 can be used as x, a, c, b, ax, and bc registers, respectively, by setting the rss bit of the psw to 1. however, use this function only for recycling the program of the 78k/iii series.
25 m pd784214y,784215y,784216y 6.2.2 control registers (1) program counter (pc) the program counter is a 20-bit register whose contents are automatically updated when the program is executed. figure 6-5. program counter (pc) format 19 0 pc (2) program status word (psw) this register holds the statuses of the cpu. its contents are automatically updated when the program is executed. figure 6-6. program status word (psw) format 15 14 13 12 11 10 9 8 uf rbs2 rbs1 rbs0 pswh 76 54 3210 s z rss note ac ie p/v 0 cy pswl psw note this flag is provided to maintain compatibility with the 78k/iii series. be sure to clear this flag to 0, except when the software for the 78k/iii series is used. (3) stack pointer (sp) this is a 24-bit pointer that holds the first address of the stack. be sure to write 0 to the higher 4 bits of this pointer. figure 6-7. stack pointer (sp) format 23 0 pc 20 0 0 0 0
26 m pd784214y,784215y,784216y 6.2.3 special function registers (sfrs) the special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. these registers are mapped to a 256-byte space of addresses 0ff00h through 0ffffh note . note on execution of the location 0 instruction. fff00h through fffffh on execution of the location 0fh instruction. caution do not access an address in this area to which no sfr is allocated. if such an address is accessed by mistake, the m m m m m PD784216Y may be in the deadlock status. this deadlock status can be cleared only by inputting the reset signal. table 6-1 lists the special function registers (sfrs). the meanings of the symbols in this table are as follows: ? symbol ............................... symbol indicating an sfr. this symbol is reserved for necs assembler (ra78k4). it can be used as a bit type sfr variable by the #pragma sfr command with the c compiler (cc78k4). ? r/w .................................... indicates whether the sfr is read-only, write-only, or read/write. r/w : read/write r : read-only w : write-only ? bit units for manipulation .. bit units in which the value of the sfr can be manipulated. sfrs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. to specify the address of this sfr, describe an even address. sfrs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. ? at reset .............................. indicates the status of the register when the reset signal has been input.
27 m pd784214y,784215y,784216y table 6-1. special function register (sfr) list (1/4) address note 1 special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w 00h note 2 0ff01h port 1 p1 r 0ff02h port 2 p2 r/w 0ff03h port 3 p3 0ff04h port 4 p4 0ff05h port 5 p5 0ff06h port 6 p6 0ff07h port 7 p7 0ff08h port 8 p8 0ff09h port 9 p9 0ff0ah port 10 p10 offoch port 12 p12 0ff0dh port 13 p13 0ff10h 16-bit timer register tm0 r 0000h 0ff11h 0ff12h capture/compare register 00 cr00 r/w 0ff13h (16-bit timer/counter) 0ff14h capture/compare register 01 cr01 0ff15h (16-bit timer/counter) 0ff16h capture/compare control register 0 crc0 00h 0ff18h 16-bit timer mode control register tmc0 0ff1ah 16-bit timer output control register toc0 0ff1ch prescaler mode register 0 prm0 0ff20h port mode register 0 pm0 ffh 0ff22h port mode register 2 pm2 0ff23h port mode register 3 pm3 0ff24h port mode register 4 pm4 0ff25h port mode register 5 pm5 0ff26h port mode register 6 pm6 0ff27h port mode register 7 pm7 0ff28h port mode register 8 pm8 0ff29h port mode register 9 pm9 0ff2ah port mode register 10 pm10 0ff2ch port mode register 12 pm12 0ff2dh port mode register 13 pm13 notes 1. when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. because each port is initialized to input mode at reset, 00h is not actually read. the output latch is initialized to 0.
28 m pd784214y,784215y,784216y table 6-1. special function register (sfr) list (2/4) address note special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ff30h pull-up resistor option register 0 pu0 r/w 00h 0ff32h pull-up resistor option register 2 pu2 0ff33h pull-up resistor option register 3 pu3 0ff37h pull-up resistor option register 7 pu7 0ff38h pull-up resistor option register 8 pu8 0ff3ah pull-up resistor option register 10 pu10 0ff3ch pull-up resistor option register 12 pu12 0ff40h clock output control register cks 0ff42h port function control register pf2 0ff4eh pull-up resistor option register puo 0ff50h 8-bit timer register 1 tm1 tm1w r 0000h 0ff51h 8-bit timer register 2 tm2 0ff52h compare register 10 (8-bit timer/counter 1) cr10 cr1w r/w 0ff53h compare register 20 (8-bit timer/counter 2) cr20 0ff54h 8-bit timer mode control register 1 tmc1 tmc1w 0ff55h 8-bit timer mode control register 2 tmc2 0ff56h prescaler mode register 1 prm1 prm1w 0ff57h prescaler mode register 2 prm2 0ff60h 8-bit timer register 5 tm5 tm5w r 0ff61h 8-bit timer register 6 tm6 0ff62h 8-bit timer register 7 tm7 tm7w 0ff63h 8-bit timer register 8 tm8 0ff64h compare register 50 (8-bit timer/counter 5) cr50 cr5w r/w 0ff65h compare register 60 (8-bit timer/counter 6) cr60 0ff66h compare register 70 (8-bit timer/counter 7) cr70 cr7w 0ff67h compare register 80 (8-bit timer/counter 8) cr80 0ff68h 8-bit timer mode control register 5 tmc5 tmc5w 0ff69h 8-bit timer mode control register 6 tmc6 0ff6ah 8-bit timer mode control register 7 tmc7 tmc7w 0ff6bh 8-bit timer mode control register 8 tmc8 0ff6ch prescaler mode register 5 prm5 prm5w 0ff6dh prescaler mode register 6 prm6 0ff6eh prescaler mode register 7 prm7 prm7w 0ff6fh prescaler mode register 8 prm8 0ff70h asynchronous serial interface mode register 1 asim1 00h 0ff71h asynchronous serial interface mode register 2 asim2 0ff72h asynchronous serial interface status register 1 asis1 0ff73h asynchronous serial interface status register 2 asis2 note when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed.
29 m pd784214y,784215y,784216y table 6-1. special function register (sfr) list (3/4) address note special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ff74h transmit shift register 1 txs1 w ffh receive buffer register 1 rxb1 r 0ff75h transmit shift register 2 txs2 w receive buffer register 2 rxb2 r 0ff76h baud rate generator control register 1 brgc1 r/w 00h 0ff77h baud rate generator control register 2 brgc2 0ff7ah oscillation mode select register cc 0ff80h a/d converter mode register adm 0ff81h a/d input select register adis 0ff83h a/d conversion result register adcr r undefined 0ff84h d/a conversion value setting register 0 dacs0 r/w 00h 0ff85h d/a conversion value setting register 1 dacs1 0ff86h d/a converter mode register 0 dam0 0ff87h d/a converter mode register 1 dam1 0ff8ch external bus type select register ebts 0ff90h serial operation mode register 0 csim0 0ff91h serial operation mode register 1 csim1 0ff92h serial operation mode register 2 csim2 0ff94h serial i/o shift register 0 sio0 0ff95h serial i/o shift register 1 sio1 0ff96h serial i/o shift register 2 sio2 0ff98h real-time output buffer register l rtbl 0ff99h real-time output buffer register h rtbh 0ff9ah real-time output port mode register rtpm 0ff9bh real-time output port control register rtpc 0ff9ch watch timer mode control register wtm 0ffa0h external interrupt rising edge enable register egp0 0ffa2h external interrupt falling edge enable register egn0 0ffa8h in-service priority register ispr r 0ffa9h interrupt select control register snmi r/w 0ffaah interrupt mode control register imc 80h 0ffach interrupt mask flag register 0l mk0l mk0 ffffh 0ffadh interrupt mask flag register 0h mk0h 0ffaeh interrupt mask flag register 1l mk1l mk1 0ffafh interrupt mask flag register 1h mk1h 0ffb0h i 2 c bus control register iiccl0 00h 0ffb2h prescaler mode register for serial clock sprm0 0ffb4h slave address register sva0 note when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed.
30 m pd784214y,784215y,784216y table 6-1. special function register (sfr) list (4/4) address note special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ffb6h i 2 c bus status register iics0 r/w 00h 0ffb8h serial shift register iic0 0ffc0h standby control register stbc 30h 0ffc2h watchdog timer mode register wdm 00h 0ffc4h memory expansion mode register mm 20h 0ffc7h programmable wait control register 1 pwc1 aah 00ffceh clock status register pcs 32h 0ffcfh oscillation stabilization time specification register osts 00h 0ffd0h- external sfr area 0ffdfh 0ffe0h interrupt control register (intwdt) wdtic 43h 0ffe1h interrupt control register (intp0) pic0 0ffe2h interrupt control register (intp1) pic1 0ffe3h interrupt control register (intp2) pic2 0ffe4h interrupt control register (intp3) pic3 0ffe5h interrupt control register (intp4) pic4 0ffe6h interrupt control register (intp5) pic5 0ffe7h interrupt control register (intp6) pic6 0ffe8h interrupt control register (intiic0/intcsi0) csic0 0ffe9h interrupt control register (intser1) seric1 0ffeah interrupt control register (intsr1/intcsi1) sric1 0ffebh interrupt control register (intst1) stic1 0ffech interrupt control register (intser2) seric2 0ffedh interrupt control register (intsr2/intcsi2) sric2 0ffeeh interrupt control register (intst2) stic2 0ffefh interrupt control register (inttm3) tmic3 0fff0h interrupt control register (inttm00) tmic00 0fff1h interrupt control register (inttm01) tmic01 0fff2h interrupt control register (inttm1) tmic1 0fff3h interrupt control register (inttm2) tmic2 0fff4h interrupt control register (intad) adic 0fff5h interrupt control register (inttm5) tmic5 0fff6h interrupt control register (inttm6) tmic6 0fff7h interrupt control register (inttm7) tmic7 0fff8h interrupt control register (inttm8) tmic8 0fff9h interrupt control register (intwt) wtic 0fffah interrupt control register (intkr) kric note when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed.
31 m pd784214y,784215y,784216y 7. peripheral hardware functions 7.1 ports the ports shown in figure 7-1 are provided to make various control operations possible. table 7-1 shows the function of each port. ports 0, 2 through 8, 10, 12 can be connected to internal pull-up resistors by software when inputting. figure 7-1. port configuration ? port 7 ? ? ? ? ? port 0 ? ? ? ? ? port 2 ? ? ? ? ? port 3 ? ? ? ? ? port 4 ? ? ? ? ? port 5 ? ? ? ? ? port 6 port 1 p70 p72 ? ? ? ? ? port 8 p80 p87 ? ? ? ? ? port 12 p120 p127 ? ? ? ? ? port 9 p90 p95 ? port 10 p100 p103 ? port 13 p130 p131 p00 p06 p10-p17 p20 p27 p30 p37 p40 p47 p50 p57 p60 p67 8
32 m pd784214y,784215y,784216y table 7-1. port functions port name pin name function specification of pull-up resistor connection by software port 0 p00-p06 ? can be set in input or output mode bit-wise can be specified bit-wise port 1 p10-p17 ? input port port 2 p20-p27 ? can be set in input or output mode bit-wise can be specified bit-wise port 3 p30-p37 ? can be set in input or output mode bit-wise can be specified bit-wise port 4 p40-p47 ? can be set in input or output mode bit-wise can be specified in 1-port units ? can directly drive leds port 5 p50-p57 ? can be set in input or output mode bit-wise can be specified in 1-port units ? can directly drive leds port 6 p60-p67 ? can be set in input or output mode bit-wise can be specified in 1-port units port 7 p70-p72 ? can be set in input or output mode bit-wise can be specified bit-wise port 8 p80-p87 ? can be set in input or output mode bit-wise can be specified bit-wise port 9 p90-p95 ? n-ch open-drain i/o port ? can be set in input or output mode bit-wise ? can directly drive leds port 10 p100-p103 ? can be set in input or output mode bit-wise can be specified bit-wise port 12 p120-p127 ? can be set in input or output mode bit-wise can be specified bit-wise port 13 p130, p131 ? can be set in input or output mode bit-wise 7.2 clock generation circuit an on-chip clock generation circuit necessary for operation is provided. this clock generation circuit has a divider circuit. if high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce the current consumption. figure 7-2. block diagram of clock generation circuit xt2 xt1 x1 x2 stop main system clock oscillation circuit subsystem clock oscillation circuit f xt watch timer, clock output function clock to peripheral hardware cpu clock (f cpu ) divider circuit prescaler prescaler standby control circuit wait control circuit f x f x 2 f xx 2 f xx 2 2 f xx 2 3 f xx selector selector
33 m pd784214y,784215y,784216y figure 7-3. example of using main system clock oscillation circuit external clock x2 x1 pd74hcu04 m v ss x2 x1 crystal resorator or ceramic resonator (1) crystal/ceramic oscillation (2) external clock figure 7-4. example of using subsystem clock oscillation circuit 32.768 khz v ss xt2 xt1 xt2 xt1 external clock pd74hcu04 m (1) crystal oscillation (2) external clock caution when using the main system clock and subsystem clock oscillation circuit, wire the dotted portions in figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of lines through which a high alternating current flows. ? always keep the potential at the ground point of the capacitor in the oscillation circuit the same as v ss . do not ground to a ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. note that the subsystem clock oscillation circuit has a low amplification factor to reduce the current consumption.
34 m pd784214y,784215y,784216y 7.3 real-time output port the real-time output function is to transfer data set in advance to the real-time output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. the pins that output the data to the external device constitute a port called a real-time output port. because the real-time output port can output signals without jitter, it is ideal for controlling a stepping motor. figure 7-5. block diagram of real-time output port internal bus real-time output port control register (rtpc) output trigger control circuit intp2 inttm1 inttm2 real-time output buffer register, high-order 4 bits (rtbh) 8 real-time output buffer register, low-order 4 bits (rtbl) 44 output latch rtp0 rtp7
35 m pd784214y,784215y,784216y 7.4 timer/counter one unit of 16-bit timers/counters and six units of timers/counters are provided. because a total of eight interrupt requests are supported, these timers/counters and timer can be used as eight units of timers/counters. table 7-2. operations of timers/counters name 16-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit timer/ timer/ timer/ timer/ timer/ timer/ timer/ item counter counter 1 counter 2 counter 5 counter 6 counter 7 counter 8 count width 8 bits 16 bits operation mode interval timer 1ch 1ch 1ch 1ch 1ch 1ch 1ch external event counter function timer output 1ch 1ch 1ch 1ch 1ch 1ch 1ch ppg output pwm output square wave output one-shot pulse output pulse width measurement 2 inputs number of interrupt requests 2111111
36 m pd784214y,784215y,784216y figure 7-6. block diagram of timers/counters (1/2) 16-bit timer/counter f xx /4 f xx /16 inttm3 ti01 ti00 edge detection circuit edge detection circuit 16-bit timer register (tm0) 16-bit capture/compare register 00 (cr00) 16-bit capture/compare register 01 (cr01) 16 16 clear inttm00 inttm01 to0 selector selector output control circuit 8-bit timer/counter 1 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 ti1 8-bit timer register 1 (tm1) 8-bit compare register 10 (cr10) 8 clear ovf inttm2 inttm1 to1 edge detection circuit selector selector output control circuit 8-bit timer/counter 2 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 ti2 tm1 8-bit timer register 2 (tm2) 8-bit compare register 20 (cr20) 8 clear ovf inttm2 to2 edge detection circuit output control circuit selector remark ovf: overflow flag
37 m pd784214y,784215y,784216y figure 7-6. block diagram of timers/counters (2/2) 8-bit timer/counter 5, 7 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 tin 8-bit timer register n (tmn) 8-bit compare register n0 (crn0) 8 clear ovf inttmn + 1 inttmn ton edge detection circuit output control circuit selector selector remark n= 5, 7 8-bit timer/counter 6, 8 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 tin tmn? 8-bit timer register n (tmn) 8-bit compare register n0 (crn0) 8 clear ovf inttmn ton edge detection circuit output control circuit selector remark n= 6, 8
38 m pd784214y,784215y,784216y 7.5 a/d converter an a/d converter converts an analog input variable into a digital signal. this microcontroller is provided with an a/d converter with a resolution of 8 bits and 8 channels (ani0 through ani7). this a/d converter is of successive approximation type and the result of conversion is stored to an 8-bit a/d conversion result register (adcr). the a/d converter can be started in the following two ways: ? hardware start conversion is started by trigger input (p03). ? software start conversion is started by setting the a/d converter mode register. one analog input channel is selected from ani0 through ani7 for a/d conversion. when a/d conversion is started by means of hardware start, conversion is stopped after it has been completed. when conversion is started by means of software start, a/d conversion is repeatedly executed, and each time conversion has been completed, an interrupt request (intad) is generated. figure 7-7. block diagram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 sample & hold circuit series resistor string voltage comparator successive approximation register (sar) a/d conversion result register (adcr) control circuit edge detection circuit intp3/p03 intad intp3 av ss av ref0 av dd internal bus selector tap selector edge detection circuit
39 m pd784214y,784215y,784216y 7.6 d/a converter a d/a converter converts an input digital signal into an analog voltage. this microcontroller is provided with a voltage output type d/a converter with a resolution of 8 bits and two channels. the conversion method is of r-2r resistor ladder type. d/a conversion is started by setting dace0 of the d/a converter mode register 0 (dam0) and dace1 of the d/ a converter mode register 1 (dam1). the d/a converter operates in the following two modes: ? normal mode the converter outputs an analog voltage immediately after it has completed d/a conversion. ? real-time output mode the converter outputs an analog voltage in synchronization with an output trigger after it has completed d/a conversion. figure 7-8. block diagram of d/a converter av ref1 av ss dacs0 8 2r 2r r r 2r 2r selector ano0 dacs1 8 2r 2r r r 2r 2r selector ano1
40 m pd784214y,784215y,784216y 7.7 serial interface three independent serial interface channels are provided. ? asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 ? clocked serial interface (csi) 1 ? 3-wire serial i/o (ioe) ?i 2 c bus interface (i 2 c) therefore, communication with an external system and local communication within the system can be simultaneously executed (refer to figure 7-9 ). figure 7-9. example of serial interface (a) uart + i 2 c PD784216Y (master) m m pd4711a m pd4711a rs-232-c driver/receiver rs-232-c driver/receiver [uart] [uart] ? port ? port rxd1 txd1 rxd2 txd2 sda0 scl0 [i 2 c] lcd pd78054y (slave) m pd78062y (slave) m v dd sda scl sda scl v dd (b) uart + 3-wire serial i/o PD784216Y (master) pd4711a rs-232-c driver/receiver [uart] ? port rxd2 txd2 pd75108 (slave) m m m si so sck port int [3-wise serial i/o] note so1 si1 sck1 intpm port note handshake line
41 m pd784214y,784215y,784216y 7.7.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial i/o mode are provided. (1) asynchronous serial interface mode in this mode, data of 1 byte following the start bit is transferred or received. because an on-chip baud rate generator is provided, a wide range of baud rates can be set. moreover, the clock input to the asck pin can be divided to define a baud rate. when the baud rate generator is used, a baud rate conforming to the midi standard (31.25 kbps) can be also obtained. figure 7-10. block diagram in asynchronous serial interface mode internal bus 8 8 8 receive buffer register 1, 2 (rxb1, rxb2) receive shift register transmit shiftregister 1, 2 (txs1, txs2) receive control parity check transmit control parity append rxd1, rxd2 txd1, txd2 asck1, asck2 daud rate generator intsr1, intsr2 intst1, intst2 selector f xx -f xx /2 5
42 m pd784214y,784215y,784216y (2) 3-wire serial i/o mode in this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. this mode is used to communicate with a device having the conventional clocked serial interface. basically, communication is established by using three lines: serial clocks (sck1 and sck2), serial data inputs (si1 and si2), and serial data outputs (so1 and so2). to connect two or more devices, a handshake line is necessary. figure 7-11. block diagram in 3-wire serial i/o mode internal bus 8 8 direction control circuit interrupt generation circuit selector serial clock counter serial clock control circuit serial i/o shift register 1, 2 (sio1, sio2) si1, si2 so1, so2 sck1, sck2 intcsi1, intcsi2 inttm2 f xx /8 f xx /16
43 m pd784214y,784215y,784216y 7.7.2 clocked serial interface (csi) in this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. (1) 3-wire serial i/o mode this mode is to communicate with devices having the conventional clocked serial interface. basically, communication is established in this mode with three lines: one serial clock (sck0) and two serial data (si0 and so0) lines. generally, a handshake line is necessary to check the reception status. figure 7-12. block diagram in 3-wise serial i/o mode 8 8 si0 so0 sck0 intcsi0 inttm2 f xx /8 f xx /16 internal bus direction control circuit interrupt generation circuit selector serial clock counter serial clock control circuit serial i/o shift register 0 (sio0) (2) i 2 c (inter ic) bus mode this mode is to communicate with devices conforming to the i 2 c bus format. this mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (scl0) and serial data bus (sda0). during transfer, a start condition, data, and stop condition can be output onto the serial data bus. during reception, these data can be automatically detected by hardware.
44 m pd784214y,784215y,784216y figure 7-13. block diagram in i 2 c bus mode internal bus 8 8 direction control circuit 8 slave address register (sva0) output latch wakeup control circuit serial i/o shift register 0 (sio0) start condition/ acknowledge detection circuit stop condition detection circuit serial clock counter serial clock control circuit interrupt generation circuit selector sda0 scl0 intiic0 to2/18-to2/68 f xx /24-f xx /178 acknowledge generation circuit 7.8 clock output function clocks of the following frequencies can be output. ? 97.7 khz/195 khz/391 khz/781 khz/1.56 mhz/3.13 mhz/6.25 mhz/12.5 mhz (main system clock: 12.5 mhz) ? 32.768 khz (subsystem clock: 32.768 khz) figure 7-14. block diagram of clock output function f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt synchronization circuit output control circuit pcl selector
45 m pd784214y,784215y,784216y 7.9 buzzer output function clocks of the following frequencies can be output as buzzer output. ? 1.5 khz/3.1 khz/6.1 khz/12.2 khz (main system clock: 12.5 mhz) figure 7-15. block diagram of buzzer output function f xx /2 10 f xx /2 11 f xx /2 12 f xx /2 13 output control circuit buz selector 7.10 edge detection function the interrupt input pins (intp0, intp1, nmi/intp2, intp3 through intp6) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. because these pins operate at an edge of the input signal, they have a function to detect an edge. moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise. pin name detectable edge noise reduction nmi either or both of rising and falling edges by analog delay intp0 through intp6 7.11 watch timer the watch timer has the following functions: ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. (1) watch timer the watch timer sets the wtif flag of the interrupt control register (wtic) at time intervals of 0.5 seconds by using the 32.768-khz subsystem clock. (2) interval timer the interval timer generates an interrupt request (inttm3) at predetermined time intervals.
46 m pd784214y,784215y,784216y figure 7-16. block diagram of watch timer f xx /2 8 prescaler f xt f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w f w 2 9 5-bit counter f w 2 5 f w 2 14 intwt inttm3 to 16-bit timer/counter selector selector selector selector 7.12 watchdog timer a watchdog timer is provided to detect a hang up of the cpu. this watchdog timer generates a non-maskable or maskable interrupt unless it is cleared by software within a specified interval time. once enabled to operate, the watchdog timer cannot be stopped by software. whether the interrupt by the watchdog timer or the interrupt input from the nmi pin takes precedence can be specified. figure 7-17. block diagram of watchdog timer f clk /2 21 f clk /2 20 f clk /2 19 f clk /2 17 f clk clear signal timer intwdt selector remark f clk : internal system clock (f xx to f xx /8)
47 m pd784214y,784215y,784216y 8. interrupt function as the servicing in response to an interrupt request, the three types shown in table 8-1 can be selected by program. table 8-1. servicing of interrupt request servicing mode entity of servicing servicing contents of pc and psw vectored interrupt software branches and executes servicing routine saves to and restores (servicing is arbitrary). from stack. context switching automatically switches register bank, saves to or restores from branches and executes servicing routine fixed area in register bank (servicing is arbitrary). macro service firmware executes data transfer between memory retained and i/o (servicing is fixed) 8.1 interrupt sources table 8-2 shows the interrupt sources available. as shown, interrupts are generated by 29 types of sources, execution of the brk instruction, or an operand error. the priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. when the macro service function is used, however, nesting always proceeds. the default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (refer to table 8-2 ).
48 m pd784214y,784215y,784216y table 8-2. interrupt sources type default source internal/ macro priority name trigger external service software brk instruction instruction execution operand error if result of exclusive or between operands byte and byte is not ffh when mov stbc, #byte or mov wdm, #byte instruction is executed non-maskable nmi pin input edge detection external intwdt overflow of watchdog timer internal maskable 0 ( highest ) intwdt overflow of watchdog timer internal 1 intp0 pin input edge detection external 2 intp1 3 intp2 4 intp3 5 intp4 6 intp5 7 intp6 8 intiic0 end of i 2 c bus transfer by csi0 internal intcsi0 end of 3-wire transfer by csi0 9 intser1 occurrence of uart reception error in asi1 10 intsr1 end of uart reception by asi1 intcsi1 end of 3-wire transfer by csi1 11 intst1 end of uart transfer by asi1 12 intser2 occurrence of uart reception error in asi2 13 intsr2 end of uart reception by asi2 intcsi2 end of 3-wire transfer by csi2 14 intst2 end of uart transfer by asi2 15 inttm3 reference time interval signal from watch timer 16 inttm00 signal indicating coincidence between 16-bit timer register and capture/compare register (cr00) 17 inttm01 signal indicating coincidence between 16-bit timer register and capture/compare register (cr01) 18 inttm1 occurrence of coincidence signal of 8-bit timer/counter 1 19 inttm2 occurrence of coincidence signal of 8-bit timer/counter 2 20 intad end of conversion by a/d converter 21 inttm5 occurrence of coincidence signal of 8-bit timer/counter 5 22 inttm6 occurrence of coincidence signal of 8-bit timer/counter 6 23 inttm7 occurrence of coincidence signal of 8-bit timer/counter 7 24 inttm8 occurrence of coincidence signal of 8-bit timer/counter 8 25 intwt overflow of watch timer 26 (lowest) intkr detection of falling edge of port 8 external remark asi : asynchronous serial interface csi : clocked serial interface
49 m pd784214y,784215y,784216y 8.2 vectored interrupt execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. so that the cpu performs interrupt servicing, the following operations are performed: ? on branching: saves the status of the cpu (contents of pc and psw) to stack ? on returning : restores the status of the cpu (contents of pc and psw) from stack to return to the main routine from an interrupt service routine, the reti instruction is used. the branch destination address is in a range of 0 to ffffh. table 8-3. vector table address interrupt source vector table address interrupt source vector table address brk instruction 003eh intst1 001ch operand error 003ch intser2 001eh nmi 0002h insr2 0020h intwdt ( non-maskable ) 0004h intcsi2 intwdt (maskable) 0006h intst2 0022h intp0 0008h inttm3 0024h intp1 000ah inttm00 0026h intp2 000ch inttm01 0028h intp3 000eh inttm1 002ah intp4 0010h inttm2 002ch intp5 0012h intad 002eh intp6 0014h inttm5 0030h intiic0 0016h inttm6 0032h intcsi0 inttm7 0034h intser1 0018h inttm8 0036h intsr1 001ah intwt 0038h intcsi1 intkr 003ah
50 m pd784214y,784215y,784216y 8.3 context switching when an interrupt request is generated or when the brkcs instruction is executed, a predetermined register bank is selected by hardware. context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (pc) and program status word (psw) to the register bank. the branch address is in a range of 0 to ffffh. figure 8-1. context switching operation when interrupt request is generated register bank n (n = 0 to 7) 0000b <7> transfer pc19-16 pc15-0 <6> exchange <5> save <2> save temporary register <1> save psw v u t w a b r5 r7 d h x c r4 r6 e l vp up <3> switching of register bank (rsb0 to rsb2 ? n) register bank n (0 to 7) (bits 8 through 11 of temporary register) <4> rss ? 0 ie ? 0 8.4 macro service this function is to transfer data between memory and a special function register (sfr) without intervention by the cpu. a macro service controller accesses the memory and sfr in the same transfer cycle and directly transfers data without loading it. because this function does not save or restore the status of the cpu, or load data, data can be transferred at high speeds. figure 8-2. macro service cpu memory sfr macro service controller read write write read internal bus
51 m pd784214y,784215y,784216y 8.5 application example of macro service (1) transmission of serial interface transfer data storage buffer (memory) data n data n? data 1 data 2 internal bus transmit shift register txs1, txs2(sfr) transfer control txd1, txd2 intst1, intst2 each time macro service request intst1 and intst2 are generated, the next transmit data is transferred from memory to txs1 and txs2. when data n (last byte) has been transferred to txs1 and txs2 (when the transmit data storage buffer has become empty), vectored interrupt request intst1 and intst2 are generated. (2) reception of serial interface receive data storage buffer (memory) data n data n? data 1 data 2 internal bus receive shift register rxb1, rxb2(sfr) reception control intsr1, intsr2 rxd1, rxd2 receive buffer register each time macro service request intsr1 and intsr2 are generated, the receive data is transferred from rxb1 and rxb2 to memory. when data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request intsr1 and intsr2 are generated.
52 m pd784214y,784215y,784216y 9. local bus interface the local bus interface can connect an external memory or i/o (memory mapped i/o) and support a memory space of 1 mbyte (refer to figure 9-1 ). figure 9-1. example of local bus interface (1) multiplexed bus mode m PD784216Y rd wr a8-a19 astb ad0-ad7 v dd address latch le q0-q7 d0-d7 oe sram cs oe we i/o1-i/o8 a0-a19 data bus address bus (2) separate bus mode v dd address bus sram data bus oe we a0-a19 cs i/o1-i/o8 m PD784216Y rd wr a0-a19 ad0-ad7
53 m pd784214y,784215y,784216y 9.1 memory expansion external program and data memory can be connected in two stages: 256k bytes and 1 mbytes. to connect the external memory, ports 4 through 6 and port 8 are used. the external memory can be connected in the following two modes: ? multiplexed bus mode : the external memory is connected by using a time-division address/data bus. the number of ports used when the external memory is connected can be reduced in this mode. ? separate bus mode : the external memory is connected by using an address bus and data bus independent of each other. because an external latch circuit is not necessary, this mode is useful for reducing the number of components and mounting area on the printed wiring board. 9.2 programmable wait wait state(s) can be inserted to the memory space (00000h through fffffh) while the rd and wr signals are active. in addition, there is an address wait function that extends the active period of the astb signal to gain the address decode time.
54 m pd784214y,784215y,784216y 10. standby function this function is to reduce the power dissipation of the chip, and can be used in the following modes: ? halt mode : stops supply of the operating clock to the cpu. this mode is used in combination with the normal operation mode for intermittent operation to reduce the average power dissipation. ? idle mode : stops the entire system with the oscillation circuit continuing operation. the power dissipation in this mode is close to that in the stop mode. however, the time required to restore the normal program operation from this mode is almost the same as that from the halt mode. ? stop mode : stops the main system clock and thereby to stop all the internal operations of the chip. consequently, the power dissipation is minimized with only leakage current flowing. ? power-saving mode : the main system clock is stopped with the subsystem clock used as the system clock. the cpu can operate on the subsystem clock to reduce the current consumption. ? power-saving halt mode : this is a standby function in the power-saving mode and stops the operation clock of the cpu, to reduce the power consumption of the entire system. ? power-saving idle mode : this is a standby function in the power-saving mode and stops the entire system except the oscillation circuit, to reduce the power consumption of the entire system. these modes are programmable. the macro service can be started from the halt mode.
55 m pd784214y,784215y,784216y figure 10-1. transition of standby status power- saving mode (operation on subsystem clock) power- saving halt mode (standby) power- saving idle mode (standby) power-saving idle mode is set. reset input power-saving halt mode is set. normal operation is restored. interrupt request note power-saving halt mode is set. reset input interrupt request note interrupt request of masked interrupt interrupt request of masked interrupt interrupt request of masked interrupt interrupt request of masked interrupt interrupt request of masked interrupt waits for oscillation stabilization normal operation (operation on main system clock) macro service halt (standby) idle (standby) stop (standby) oscillation stabilization time expires macro service request end of one processing end of macro service macro service request end of one processing interrupt request note reset input sets halt mode sets idle mode reset input interrupt request note sets stop mode reset input interrupt request note note only interrupt requests that are not masked
56 m pd784214y,784215y,784216y 11. reset function when a low-level signal is input to the reset pin, the system is reset, and each hardware unit is initialized (reset). during the reset period, oscillation of the main system clock is unconditionally stopped. consequently, the current consumption of the entire system can be reduced. when the reset signal goes high, the reset status is cleared, oscillation stabilization time (41.9 ms at 12.5 mhz) elapses, the contents of the reset vector table are set to the program counter (pc), execution branches to an address set to the pc, and program execution is started from that branch address. therefore, the program can be reset and started from any address. figure 11-1. oscillation of main system clock during reset period oscillation is unconditionally stopped during reset period. oscillation stabilization time main system clock oscillation circuit f clk reset input the reset input pin has an analog delay noise rejection circuit to prevent malfunctioning due to noise. figure 11-2. accepting reset signal analog delay analog delay analog delay oscillation stabilization time reset input internal reset signal internal clock
57 m pd784214y,784215y,784216y 12. instruction set (1) 8-bit instructions (the instructions in parentheses are combinations realized by describing a as r) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chikl, chkla table 12-1. instruction list by 8-bit addressing second operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r' saddr' !!addr24 [saddrp] pswl [whlC] first operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) note 1,6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tdeC] (add) note 1 movm note 4 notes 1. the operands of addc, sub, subc, and, or, xor, and cmp are the same as that of add. 2. either the second operand is not used, or the second operand is not an operand address. 3. the operands of rol, rorc, rolc, shr, and shl are the same as that of ror. 4. the operands of xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as that of movm. 5. the operands of xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as that of movbk. 6. the code length of some instructions having saddr2 as saddr in this combination is short.
58 m pd784214y,784215y,784216y (2) 16-bit instructions (the instructions in parentheses are combinations realized by describing ax as rp) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 12-2. instruction list by 16-bit addressing second operand #word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 rp' saddrp' !!addr24 [saddrp] first operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) note 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. the operands of subw and cmpw are the same as that of addw. 2. either the second operand is not used, or the second operand is not an operand address. 3. the code length of some instructions having saddrp2 as saddrp in this combination is short. 4. the operands of muluw and divux are the same as that of mulw.
59 m pd784214y,784215y,784216y (3) 24-bit instructions (the instructions in parentheses are combinations realized by describing whl as rg) movg, addg, subg, incg, decg, push, pop table 12-3. instruction list by 24-bit addressing second operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note rg' first operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note either the second operand is not used, or the second operand is not an operand address.
60 m pd784214y,784215y,784216y (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 12-4. bit manipulation instructions second operand cy saddr.bit sfr.bit /saddr.bit /sfr. bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit first operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note either the second operand is not used, or the second operand is not an operand address.
61 m pd784214y,784215y,784216y (5) call and return/branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 12-5. call and return/branch instructions operand of instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none address basic instruction bc note call call call call call call call callf callf brkcs brk br br br br br br br br ret retcs reti retcsb retb compound instruction bf bt btclr bfset dbnz note the operands of bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs
62 m pd784214y,784215y,784216y 13. package drawings 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0?.2 0.630?.008 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 16.0?.2 0.630?.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009?.002 p100gc-50-7ea-2 k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 p 1.45 0.057 +0.05 ?.04 +0.03 ?.07 b c d j h i g f p n l k m q r detail of lead end q 0.125?.075 0.005?.003 r s 1.7 max. 55? 55? 0.067 max. +0.001 ?.003 m 1 25 26 50 100 76 75 51
63 m pd784214y,784215y,784216y j n m p 80 81 50 100 pin plastic qfp (14 20) 100 1 31 30 51 g detail of lead end s 5 5 c d a b h q k l f m i p100gf-65-3ba1-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.6 0.30 0.10 0.15 20.0 0.2 0.929 0.016 0.031 0.024 0.006 0.026 (t.p.) 0.795 note m n 0.10 0.15 1.8 0.2 0.65 (t.p.) 0.006 0.031 +0.009 ?.008 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.012 0.551 0.8 0.2 0.071 p 2.7 0.106 0.693 0.016 17.6 0.4 0.8 +0.008 ?.009 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.004 ?.003 0.004
64 m pd784214y,784215y,784216y appendix a. development tools the following development tools are available for supporting development of a system using the m PD784216Y. language processor software ra78k4 note 1 assembler package common to 78k/iv series cc78k4 note 1 c compiler package common to 78k/iv series cc78k4-l note 1 c compiler library source file common to 78k/iv series flash memory writing tool pending dedicated flash writer debugging tool ie-784000-r in-circuit emulator common to 78k/iv series ie-784000-r-bk break board common to 78k/iv series ie-784218-r-em1 emulation board for evaluation of m PD784216Y subseries ie-784000-r-em ie-70000-98-if-b interface adapter when pc-9800 series (except notebook type) is used as host machine ie-70000-98n-if interface adapter and cable when notebook type pc-9800 series is used as host machine ie-70000-pc-if-b interface adapter when ibm pc/at tm is used as host machine ie-78000-r-sv3 interface adapter and cable when ews is used as host machine ep-78064gc-r emulation probe for 100-pin plastic qfp (fine pitch) (14 14 mm) common to m PD784216Y subseries ep-78064gf-r emulation probe for 100-pin plastic qfp (14 20 mm) common to m PD784216Y subseries ev-9500gc-100 adapter mounted on board of target system created for 100-pin plastic qfp (fine pitch) (14 14 mm) ev-9200gf-100 socket mounted on board of target system created for 100-pin plastic qfp (14 20 mm) sm78k4 note 2 system simulator common to 78k/iv series id78k4 note 2 integrated debugger for ie-784000-r df784218 note 3 device file for m PD784216Y subseries real-time os rx78k/iv note 3 real-time os for 78k/iv series mx78k4 note 4 os for 78k/iv series remark ra78k4, cc78k4, sm78k4, and id78k4 are used in combination with df784218.
65 m pd784214y,784215y,784216y notes. 1. ? pc-9800 series (ms-dos tm ) base ? ibm pc/at and compatible machine (pc dos tm , windows tm , ms-dos, ibm dos tm ) base ? hp9000 series 700 tm (hp-ux tm ) base ? sparcstation tm (sunos tm ) base ? news tm (news-os tm ) base 2. ? pc-9800 series (ms-dos+windows) base ? ibm pc/at and compatible machine (pc dos, windows, ms-dos, ibm dos) base ? hp9000 series 700 (hp-ux) base ? sparcstation (sunos) base 3. ? pc-9800 series (ms-dos) base ? ibm pc/at and compatible machine (pc dos, windows, ms-dos, ibm dos) base ? hp9000 series 700 (hp-ux) base ? sparcstation (sunos) base 4. ? pc-9800 series (ms-dos) base ? imb pc/at and compatible machine (pc dos, windows, ms-dos, ibm dos) base
66 m pd784214y,784215y,784216y appendix b. related documents documents related to device document name document no. japanese english m pd784214y, 784215y, 784216y preliminary product information u11725j this document m pd78f4216y preliminary product information planned planned m pd784216, 784216y subseries users manual - hardware planned planned m PD784216Y subseries special function register table planned C 78k/iv series users manual - instruction u10905j ieu-1386 78k/iv series instruction table u10594j C 78k/iv series instruction set u10595j C 78k/iv series application note - software basics u10095j u10095e documents related to development tools (users manuals) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k series library source file eeu-777 C pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller - pc-9800 series (ms-dos) base eeu-704 eeu-1291 pg-1500 controller - ibm pc series (pc dos) base eeu-5008 u10540e ie-784000-r eeu-5004 eeu-1534 ie-784218-r-em1 planned C ep-78064 eeu-934 eeu-1469 sm78k4 system simulator - windows base reference u10093j u10093e sm78k series system simulator external component u10092j u10092e user open interface specification id78k4 integrated debugger reference u10440j u10440e caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of a document for designing.
67 m pd784214y,784215y,784216y documents related to embedded software (users manual) document name document no. japanese english 78k/iv series real-time os basics u10603j C installation u10604j C debugger u10364j C 78k/iv series os mx78k4 planned C other documents document name document no. japanese english ic semiconductor device package manual c10943x semiconductor device mounting technology manual u10535j 10535e quality grades on nec semiconductor devices iei-620 iei-1209 nec semiconductor device reliability/quality control system u10983j u10983e electrostatic discharge (esd) test mem-539 C guide to quality assurance for semiconductor devices mei-603 mei-1202 guide to microcontroller-related products by third parties mei-604 C caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of a document for designing.
68 m pd784214y,784215y,784216y [memo]
69 m pd784214y,784215y,784216y notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
70 m pd784214y,784215y,784216y nec electronics inc. (u.s.) mountain view, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby sweden tel: 8-63 80 820 fax: 8-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 3
71 m pd784214y,784215y,784216y caution purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. iebus is a trademark of nec corp. ms-dos and windows are trademarks of microsoft corp. ibm dos, pc/at, and pc dos are trademarks of ibm corp. hp9000 series 700 and hp-ux are trademarks of hewlett-packard co. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corp.
72 m pd784214y,784215y,784216y the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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